1. Field of the Invention
This invention relates to computer systems and, more particularly, to arbitration mechanisms for selecting one or more inputs for output.
2. Description of the Related Art
Many systems use some mechanism to choose between two or more inputs. In some computer systems, a system controller may arbitrate a winning bus between two or more buses using a bus arbitration scheme. In a router system, a switching unit may choose to output a single winning input from multiple inputs using a round robin arbitration scheme, for example.
In a round robin arbiter having multiple inputs, the arbiter may choose to output a single winning input in a given cycle based upon some predefined selection order. Then on the next arbitration cycle, the winning input from the previous cycle may have the lowest priority. Thus, the arbiter may take turns sequentially selecting each input in successive cycles.
However, some systems may require more than one input to be selected in a given cycle. Thus, one method of selecting more than one input in a given cycle may be to use multiple parallel arbiters having different ordering rules. However, this may not be efficient in terms of gate counts or area, particularly when the arbiter is implemented on an integrated circuit.